Technical reference · 12 September 2026
| Specification | Configuration |
|---|---|
| Radio / platform | Wi-Fi 6E | three two-stream radio cells |
| Theoretical PHY reference | 573 / 2402 / 2402 Mb/s by band |
| Host / processor | IPQ5018; dual-core Cortex-A53 at 1 GHz; 512 MB DDR3L |
| Channel / network configuration | 1 x 2.5GbE + 1 x 1GbE; USB 2.0; UART |
| RF / power | 2 x U.FL at 2.4 GHz + 4 x MMCX high-band; DC 12-56 V |
| Mechanical / environment | Compact embedded gateway; matched PoE configuration |
| Parameter | Pulse B6-03 |
|---|---|
| Processor and memory | IPQ5018; Cortex-A53 platform; 512 MB DDR3L |
| System storage | 8 MB NOR and 128 MB NAND |
| Network interfaces | One 2.5GbE and one 1GbE port |
| Engineering interfaces | USB 2.0, SGMII and UART |
| RF allocation | Two U.FL at 2.4 GHz; two MMCX at 5 GHz and two MMCX at 6 GHz |
| Channel profiles | 20/40 MHz at 2.4 GHz; 20/40/80/160 MHz at 5 and 6 GHz |
| Power integration | 12-56 V DC input; matched active/passive PoE configuration |
| Mechanical and environment | 122 x 105 x 21 mm including heatsink; -40 to +70 C operating |
Model-specific datasheet reference points for RF design. TX is conducted power per RF chain; RX is input sensitivity. Configure channel, output power and antenna gain for the operating country.
| MCS | TX / chain (dBm) | RX sensitivity (dBm) |
|---|---|---|
| MCS0 | 25.0 | -84.0 |
| MCS1 | 25.0 | -82.0 |
| MCS2 | 24.0 | -80.0 |
| MCS3 | 23.5 | -78.0 |
| MCS4 | 23.0 | -75.0 |
| MCS5 | 22.5 | -72.0 |
| MCS6 | 22.0 | -70.0 |
| MCS7 | 21.5 | -68.0 |
| MCS8 | 21.0 | -65.0 |
| MCS9 | 20.0 | -63.0 |
| MCS10 | 19.5 | -60.0 |
| MCS11 | 19.0 | -57.0 |
Reference tolerance: ±2 dB.
| MCS | TX / chain (dBm) | RX sensitivity (dBm) |
|---|---|---|
| MCS0 | 26.0 | -84.0 |
| MCS1 | 25.0 | -82.0 |
| MCS2 | 24.5 | -80.0 |
| MCS3 | 24.5 | -78.0 |
| MCS4 | 24.0 | -75.0 |
| MCS5 | 23.0 | -72.0 |
| MCS6 | 22.5 | -70.0 |
| MCS7 | 22.0 | -68.0 |
| MCS8 | 21.0 | -65.0 |
| MCS9 | 20.0 | -63.0 |
| MCS10 | 19.5 | -60.0 |
| MCS11 | 19.0 | -57.0 |
Reference tolerance: ±2 dB.
Use the complete board-specific system image for Pulse B6-03, including its bootloader, device tree, Ethernet switch/PHY configuration and radio calibration. Preserve the existing flash partition map and calibration partitions before an upgrade. Match the recovery procedure to the board revision and serial header.
| Integration item | Model-specific preparation |
|---|---|
| Platform | IPQ5018; dual-core Cortex-A53 at 1 GHz; 512 MB DDR3L |
| Network verification | 1 x 2.5GbE + 1 x 1GbE; USB 2.0; UART |
| Image identity | Record release/build, board revision, image checksum and the partition layout. |
| OpenWrt / QSDK workflow | Select a board-targeted build approved for the delivered assembly; radio-driver support is only one part of the complete image. |
| First boot | Capture the UART boot log; verify memory, flash, Ethernet link negotiation and each installed radio. |
Use the following commissioning procedure for Pulse B6-03. This is a test method, separate from the theoretical PHY specifications and datasheet RF references above.
| Step | Record and verify |
|---|---|
| Baseline | Model/revision, firmware build, host CPU, uplink speed, channel width, country profile, antennas and client spatial streams. |
| Link verification | Capture negotiated PHY, RSSI per chain and noise/retry statistics before sustained traffic. |
| Wired reference | Measure the wired path first; select a server link appropriate to 573 / 2402 / 2402 Mb/s by band. |
| Traffic test | Run TCP in each direction, then concurrent clients; record duration, CPU load, temperatures and retransmissions. |
| Site acceptance | Repeat at the intended mounting positions; save results with the exact configuration for comparison. |
524WiFi™ engineering support · Tomorrow Systems®